1. Field of the Invention
The present invention relates generally to electronic circuits, and more particularly but not exclusively to the design and manufacture of integrated circuits.
2. Description of the Background Art
In recent years, integrated circuits have been increasing in complexity and in the degree of integration with each generation. Integrated circuits generally include multiple patterned conducting, semiconducting, and dielectric layers formed on a substrate or wafer by a combination of photolithographic, etching and deposition techniques. The increased complexity of latest generation of devices require finer and more accurately formed wiring and interconnects or vias. Thus, before each successive layer is formed, the underlying surface or present layer is planarized by, for example, chemical-mechanical polishing or planarization (CMP). CMP produces a substantially flat surface across the layer provided the layer has a substantially uniform density in a distribution or spacing of elements or features across the surface.
Although CMP can flatten small imperfections relatively well, differences in the size and spacing of various elements in a patterned layer can often yield significant differences in density of the layer, resulting in non-uniform planarization across the surface of the substrate. This problem is illustrated with reference to the schematic cross-sectional views of FIGS. 1A and 1B. In FIG. 1A, an interlevel dielectric (ILD) layer 135 is formed over a metal level 130. Metal level 130 includes patterned metal lines 110 (i.e., 110-1, 110-2) separated by a dielectric 132. Depending on the spacing between metal lines 110, chemical-mechanical polishing of the surface of interlevel dielectric layer 135 may result in an indentation 131 in regions between metal lines 110.
To address the aforementioned planarization problem, designers may incorporate dummy metal patterns in metal levels. The number of dummy metal patterns to be added to a metal level may depend on pattern density requirements. Dummy metal patterns, which are also referred to as “waffles” or “dummy fill patterns,” allow the thickness of an interlevel dielectric to remain consistent during CMP. Other than to provide structural support, dummy metal patterns have no electrical function in the integrated circuit. That is, current is not flown through dummy metal patterns. In FIG. 1B, a dummy metal pattern 120 is added between metal lines 110. Dummy metal pattern 120 has no electrical function and is accordingly left electrically floating.
Computer aided design programs may be employed to create a process model that describes the behavior of an integrated circuit. Process models allow designers to simulate the integrated circuit for testing, optimization, and other purposes. In a typical design flow, the dummy metal patterns may be added or drawn to the circuit layout just prior to tape out after the timing closure step is complete. Although there is no current flow through a dummy metal pattern, it may interact with other nets affecting the parasitic capacitance, which impacts circuit timing.
One way to account for the effects of dummy metal patterns is to add them to the circuit layout prior to circuit extraction for timing. However, conventional high capacity parasitic extraction tools, such as the Assura™ and QX™ software from Cadence Design systems and the Caliber™ software from Mentor Graphics, cannot accurately account for floating geometries. The extraction may result in pessimistic capacitance values, which can be up to 15% error in some cases. Adding dummy metal patterns to the circuit layout before extraction may reduce the capacity of the extraction software as well. Furthermore, in a number of cases, simulation/timing analysis tools are not capable of handling capacitors to floating nets, requiring a reduction step to eliminate the floating capacitors. Simply removing floating capacitors may cause the circuit timing results to be incorrect. An alternative solution to this problem may be to decouple capacitors prior to eliminating the floating capacitors. However, In this case, the capability to simulate the effect of coupling noise is lost.
Some pattern density simulation tools, such as the Champgeo™ software from UbiTech, Inc., accept process parameters and a layout to simulate for oxide variation across the die. However, the resulting process model is specific to particular layouts and must be derived every time the layout is changed.
The use of high-density plasma or new polishing techniques in the manufacture of integrated circuits can reduce the metal density requirements for CMP, thus lessening the need for dummy metal patterns in the first place. However, this approach may necessitate relatively expensive process changes. Conventional field solver tools can accurately account for floating parasitic effects due to dummy metal patterns. However, these field solver tools have limited capacity, and are not usually practical for use on large circuits. Manually adding dummy metal patterns or generating them during extraction increases the run time.